1. Technical Field
The present invention relates to a semiconductor package and a semiconductor package module having the same.
2. Description of the Related Art
In a semiconductor industry, one of the main tendencies of a technology development has focused on the reduction in a size of a semiconductor device. Even in the semiconductor package field, with the sudden increase in a demand of a small computer, portable electronic devices, or the like, a semiconductor package such as a fine pitch ball grid array (FBGA) package or a chip scale package (CSP), or the like, capable of implementing a plurality of pins while being formed at a small size have been developed.
The semiconductor packages such as the fine pitch ball grid array package, the chip scale package, or the like, that are being currently developed has physical advantages such as miniaturization, lightness, or the like. However, the semiconductor packages do not yet secure reliability equivalent to a plastic package according to the prior art and have the reduced competitive price due to the increased cost of materials consumed during a production process and the increased processing cost.
In particular, a representative type of the current chip scale package, a so-called micro ball grid array (micro BGA (μBGA)) has excellent characteristics more than the fine pitch ball grid array or the chip scale package, but has also the reduced reliability and competitive price.
In order to overcome the disadvantages, as one type of the developed packages, there is a so-called wafer level chip scale package (wafer level CSP (WL-CSP)) using redistribution or rerouting of bonding pails of semiconductor chips formed on a wafer.
The wafer level chip scale package using the redistribution has a structural feature that the bonding pads on the semiconductor substrate is directly redistributed with other pads having a larger size and then, external connection terminals such as solder balls are formed thereon.
Meanwhile, the semiconductor package according to the prior art is disclosed in Korean Patent Laid-Open Publication No. 2011-0032158.
The semiconductor package according to the prior art may be configured by a multilayer of two layers or more according to expandability of rerouting patterns. As such, the process cost, the number of processes, and the process time may be increased, due to the multilayer manufacturing of the semiconductor package.